This application relates generally to integrated circuit design and simulation and, more particularly, to techniques for determining the effect of within die variations on leakage in integrated circuits.
With shrinking process node sizes, the inherent effect of process variations is playing a larger factor in defining the behavior of a circuit. Conventional Analysis techniques can no longer claim accuracy if they do not capture the effects of process variations. There are two factors that are becoming critical in this respect: Leakage is becoming dominant in overall power consumption; and leakage power has exponential dependency on critical process parameters. Leakage power can vary by an order of magnitude due to variation of process parameters; for instance, leakage power can vary by up to a factor of 12 for a 20% variation in effective length of a transistor. Although the absolute magnitude of a process variation (such an oxide thickness, gate length, gate width, doping density, etc.) may be the same, the relative magnitude increases greatly as device sizes shrink, so that a variation that is negligible at, say, a micron, becomes far more significant at half that size. Consequently, it becomes very imperative to factor in the effects of process variations, especially in the 45 nm and below process nodes.
Analysis tools working on standard cell-based designs typically work on standard cell models for leakage. These models may be capable of representing the effects of process variations on leakage power computation, including representing correlation of leakage power between various states. Typically, the models store the data of the effect of process variations on leakage in terms of sensitivities. One common method would be to calculate sensitivity of the log of leakage power to process parameters. In this technique, S Sensitivity to process parameter p will in general be defined as follows:
      S    =                            log          ⁡                      [                          I              ⁡                              (                                  p                  1                                )                                      ]                          -                  log          ⁡                      [                          I              ⁡                              (                                  p                  0                                )                                      ]                                                p          1                -                  p          0                      ,where p0 is the nominal value of process parameter, and p1 is the value of process parameter after variation.
Since Within-Die (WID) variations need to be considered separately for each transistor, we need to take the cumulative effect. For the nth transistor, this would be.
            S      n        =                            log          ⁡                      [                          I              ⁡                              (                                  p                  1                                )                                      ]                          -                  log          ⁡                      [                          I              ⁡                              (                                  p                  0                                )                                      ]                                                p          1                -                  p          0                      ,Once the sensitivities for all the transistors are available, sensitivity of leakage to normalized WID variation will be,
                              S          WID                =                                            ∑                              n                =                1                            N                        ⁢                                                  ⁢                                          (                                                      S                    n                                    ⁢                                      σ                    n                                                  )                            2                                                          (        1        )            Where N is the number of transistors in the cell and σn represents the standard deviation of the process parameter for the nth transistor. For more detail, see, for example, Kenichi Okada, Kento Yamaoka, and Hidetoshi Onodera “A Statistical Gate Delay Model Considering Intra-Gate Variability”, ICCAD-03.
Process variations can be classified into two broad buckets: Die-to-Die (D2D) variations and Within-Die (WID) variations. The effect of each of these needs to be computed and specified as part of the models in terms of sensitivities of the leakage current, so that the analysis tool can accurately factor for these effects during analysis.
WID variation effect is very runtime intensive to compute. As the within-die variations can be random in occurrence and amount across a chip, their effects on all the elements of the circuit need to be considered. A typical technique used for computing the effect of process variations is to perturb the various process parameters independently, measure the effect of these perturbations on the leakage power, and then use the non-perturbed and the perturbed library leakage data to generate sensitivities of the library leakage data to variations. For D2D variations, one additional simulation is required per process-parameter under consideration, so if there are 5 process parameters being considered, the runtime cost goes up to 5× the runtime for nominal leakage measurement; but for WID variations, since the variations have to be considered on a per-transistor basis, the runtime cost becomes prohibitive.
To understand this, we need to see that characterization for WID effects involves perturbation of each individual transistor in a given subcircuit, and computing the effect of that to generate the sensitivity of the cell to WID variations. For example, if a subcircuit had 20 transistors, and we are looking at the effect of variation of 5 process parameters as in the case above, then, ifNumber of simulations for generation of nominal timing data=x,Then,Number of simulations for generation of WID variations sensitivity=20*5x=100x. This is a considerable increase runtime overhead. Such simulations are already typically very computational intensive; and by taking the WID variations into account, what previously may have already been a very substantial run time of, say, a day, can now become weeks.
Consequently, there is room for improvement in the techniques available for incorporating the effects within die variations.